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1999 microchip technology inc. preliminary ds41106a-page 1 devices included in this data sheet: ? pic16c712 ? pic16c716 microcontroller core features: ? high-performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? interrupt capability (up to 7 internal/external interrupt sources) ? eight level deep hardware stack ? direct, indirect and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? brown-out detection circuitry for brown-out reset (bor) ? programmable code-protection ? power saving sleep mode ? selectable oscillator options ? low-power, high-speed cmos eprom technology ? fully static design ? in-circuit serial programming ? (icsp) ? wide operating voltage range: 2.5v to 5.5v ? high sink/source current 25/25 ma ? commercial, industrial and extended temperature ranges ? low-power consumption: - < 2 ma @ 5v, 4 mhz - 22.5 m a typical @ 3v, 32 khz -< 1 m a typical standby current pin diagrams peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm module ? capture is 16-bit, max. resolution is 12.5 ns, compare is 16-bit, max. resolution is 200 ns, pwm maximum resolution is 10-bit ? 8-bit multi-channel analog-to-digital converter device program memory data memory pic16c712 1k 128 pic16c716 2k 128 pic16c712 ra2/an2 ra4/t0cki rb0/int rb1/t1oso/t1cki ra0/an0 osc1/clkin rb7 rb6 1 2 3 4 5 6 7 18 17 16 15 14 13 12 8 9 11 10 18-pin pdip, soic, windowed cerdip mclr /v pp ra3/an3/v ref rb2/t1osi rb3/ccp1 rb4 rb5 ra1/an1 v dd osc2/clkout v ss pic16c716 pic16c712 ra2/an2 ra4/t0cki rb0/int rb1/t1oso/t1cki ra0/an0 osc1/clkin rb7 rb6 1 2 3 4 5 6 7 20 19 18 17 16 15 14 8 9 13 12 20-pin ssop mclr /v pp ra3/an3/v ref rb2/t1osi rb3/ccp1 rb4 rb5 ra1/an1 v dd osc2/clkout v ss pic16c716 10 v ss v dd 11 pic16c712/716 8-bit cmos microcontrollers with a/d converter and capture/compare/pwm
pic16c712/716 ds41106a-page 2 preliminary 1999 microchip technology inc. pic16c7xx family of devices key features picmicro ? mid-range reference manual (ds33023) pic16c712 pic16c716 operating frequency dc - 20 mhz dc - 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) program memory (14-bit words) 1k 2k data memory (bytes) 128 128 interrupts 7 7 i/o ports ports a,b ports a,b timers 3 3 capture/compare/pwm modules 1 1 8-bit analog-to-digital module 4 input channels 4 input channels pic16c710 pic16c71 pic16c711 pic16c712 pic16c715 pic16c716 pic16c72a pic16c73b clock maximum frequency of operation (mhz) 20 20 20 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 1k 1k 2k 2k 2k 4k data memory (bytes) 36 36 68 128 128 128 128 192 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr1 tmr2 tmr0 tmr0 tmr1 tmr2 tmr0 tmr1 tmr2 tmr0 tmr1 tmr2 capture/compare/ pwm module(s) 1 1 1 2 serial port(s) (spi/i 2 c, usart) spi/i 2 cspi/i 2 c, usart a/d converter (8-bit) channels 444 4 4 4 55 features interrupt sources 4 4 4 7 4 7 8 11 i/o pins 13 13 13 13 13 13 22 22 voltage range (volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 in-circuit serial programming yes yes yes yes yes yes yes yes brown-out reset yes yes yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin sdip, soic, ssop 28-pin sdip, soic
1999 microchip technology inc. preliminary ds41106a-page 3 pic16c712/716 table of contents 1.0 device overview............................................................................................................. ..................................... 5 2.0 memory organization ......................................................................................................... ................................. 9 3.0 i/o ports ................................................................................................................... ......................................... 21 4.0 timer0 module............................................................................................................... .................................... 29 5.0 timer1 module............................................................................................................... .................................... 31 6.0 timer2 module............................................................................................................... .................................... 36 7.0 capture/compare/pwm (ccp) module(s) ......................................................................................... ............... 39 8.0 analog-to-digital converter (a/d) module .................................................................................... ..................... 45 9.0 special features of the cpu ................................................................................................. ............................ 51 10.0 instruction set summary .................................................................................................... ............................... 67 11.0 development support........................................................................................................ ................................ 69 12.0 electrical characteristics ................................................................................................. .................................. 75 13.0 dc and ac characteristics graphs and tables ................................................................................ ................ 91 14.0 packaging information...................................................................................................... ................................. 93 revision history .............................................................................................................. ............................................. 99 conversion considerations ..................................................................................................... ..................................... 99 migration from base-line to mid-range devices ................................................................................. ......................... 99 index .......................................................................................................................... ................................................. 101 on-line support................................................................................................................ .......................................... 105 reader response ................................................................................................................ ....................................... 106 pic16c712/716 product identification system .................................................................................... ....................... 107 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic16c712/716 ds41106a-page 4 preliminary 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 5 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro? mid-range reference manual, (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there are two devices (pic16c712, pic16c716) cov- ered by this datasheet. figure 1-1 is the block diagram for both devices. the pinouts are listed in table 1-1. figure 1-1: pic16c712/716 block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb rb0/int rb1/t1oso/t1cki rb2/t1osi rb3/ccp1 rb4 rb5 rb6 rb7 8 8 brown-out reset note 1: higher order bits are from the status register. ccp1 a/d timer0 timer1 timer2 ra4/t0cki ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3 1k x 14 128 x 8 or 2k x 14
pic16c712/716 ds41106a-page 6 preliminary ? 1999 microchip technology inc. table 1-1 pic16c712/716 pinout description pin pic16c712/716 pin buffer name dip, soic ssop type type description mclr /v pp mclr v pp 44 i p st master clear (reset) input. this pin is an active low reset to the device. programming voltage input osc1/clkin osc1 clkin 16 18 i i st cmos oscillator crystal input or external clock source input. st buffer when configured in rc mode. cmos otherwise. external clock source input. osc2/clkout osc2 clkout 15 17 o o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. porta is a bi-directional i/o port. ra0/an0 ra0 an0 17 19 i/o i ttl analog digital i/o analog input 0 ra1/an1 ra1 an1 18 20 i/o i ttl analog digital i/o analog input 1 ra2/an2 ra2 an2 11 i/o i ttl analog digital i/o analog input 2 ra3/an3/v ref ra3 an3 v ref 22 i/o i i ttl analog analog digital i/o analog input 3 a/d reference voltage input. ra4/t0cki ra4 t0cki 33 i/o i st/od st digital i/o. open drain when configured as output. timer0 external clock input legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels od = open drain output sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 7 portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int rb0 int 67 i/o i ttl st digital i/o external interrupt rb1/t1oso/t1cki rb1 t1oso t1cki 78 i/o o i ttl st digital i/o timer1 oscillator output. connects to crystal in oscillator mode. timer1 external clock input. rb2/t1osi rb2 t1osi 89 i/o i ttl digital i/o timer1 oscillator input. connects to crystal in oscillator mode. rb3/ccp1 rb3 ccp1 910 i/o i/o ttl st digital i/o capture1 input, compare1 output, pwm1 output. rb4 10 12 i/o ttl digital i/o interrupt on change pin. rb5 11 12 i/o ttl digital i/o interrupt on change pin. rb6 12 13 i/o i ttl st digital i/o interrupt on change pin. icsp programming clock. rb7 13 14 i/o i/o ttl st digital i/o interrupt on change pin. icsp programming data. v ss 5 5, 6 p ground reference for logic and i/o pins. v dd 14 15, 16 p positive supply for logic and i/o pins. legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels od = open drain output sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver table 1-1 pic16c712/716 pinout description (c ont.d) pin pic16c712/716 pin buffer name dip, soic ssop type type description
pic16c712/716 ds41106a-page 8 preliminary ? 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 9 2.0 memory organization there are two memory blocks in each of these picmicro ? microcontroller devices. each block (pro- gram memory and data memory) has its own bus so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16c712/716 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. pic16c712 has 1k x 14 words of program memory and pic16c716 has 2k x 14 words of program memory. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack of the pic16c712 figure 2-2: program memory map and stack of pic16c716 pc<12:0> 13 0000h 0004h 0005h 03ffh 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw 0400h user memory space pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw user memory space
pic16c712/716 ds41106a-page 10 preliminary ? 1999 microchip technology inc. 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 (not implemented) = 11 ? bank3 (not implemented) each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some high use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly through the file select register fsr (section 2.5). figure 2-3: register file map rp1 (1) rp0 (status<6:5>) note 1: maintain this bit clear to ensure upward compati- bility with future products. unimplemented data memory locations, read as '0'. note 1: not a physical register. file address file address 00h indf (1) indf (1) 80h 01h tmr0 option_reg 81h 02h pcl pcl 82h 0 3 h s tat u s s tat u s 8 3 h 04h fsr fsr 84h 05h porta trisa 85h 06h portb trisb 86h 07h dataccp trisccp 87h 08h 88h 09h 89h 0ah pclath pclath 8ah 0bh intcon intcon 8bh 0ch pir1 pie1 8ch 0dh 8dh 0eh tmr1l pcon 8eh 0fh trm1h 8fh 10h t1con 90h 11h trm2 91h 12h t2con pr2 92h 13h 93h 14h 94h 15h ccpr1l 95h 16h ccpr1h 96h 17h ccp1con 97h 18h 98h 19h 99h 1ah 9ah 1bh 9bh 1ch 9ch 1dh 9dh 1eh adres 9eh 1fh adcon0 adcon1 9fh 20h general purpose registers 96 bytes general purpose registers 32 bytes a0h bfh c0h 7fh ffh bank 0 bank 1
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 11 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is give in table 2-1. the special function registers can be classified into two sets; core (cpu) and peripheral. those registers asso- ciated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in that peripheral feature section. table 2-1 special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (4) bank 0 00h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h pcl (1) program counter's (pc) least significant byte 0000 0000 0000 0000 03h status (1) irp (4) rp1 (4) rp0 to pd zdcc rr01 1xxx rr0q quuu 04h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta (5,6) (7) porta data latch when written: porta pins when read --xx xxxx --xu uuuu 06h portb (5,6) portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h dataccp (7) (7) (7) (7) (7) dccp (7) dt1ck xxxx xxxx xxxx xuxu 08h-09h unimplemented 0ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 0dh unimplemented 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h-14h 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h-1dh unimplemented 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 4: the irp and rp1 bits are reserved. always maintain these bits clear. 5: on any device reset, these pins are configured as inputs. 6: this is the value that will be in the port output latch. 7: reserved bits; do not use.
pic16c712/716 ds41106a-page 12 preliminary ? 1999 microchip technology inc. bank 1 80h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl (1) program counter's (pc) least significant byte 0000 0000 0000 0000 83h status (1) irp (4) rp1 (4) rp0 to pd zdcc rr01 1xxx rr0q quuu 84h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa (7) porta data direction register --x1 1111 --x1 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisccp (7) (7) (7) (7) (7) tccp (7) tt1ck xxxx x1x1 xxxx x1x1 88h-89h unimplemented 8ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 -0-- -000 8dh unimplemented 8eh pcon por bor ---- --qq ---- --uu 8fh-91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h-9eh unimplemented 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 4: the irp and rp1 bits are reserved. always maintain these bits clear. 5: on any device reset, these pins are configured as inputs. 6: this is the value that will be in the port output latch. 7: reserved bits; do not use. table 2-1 special function register summary (c ont.d) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (4)
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 13 2.2.2.1 status register the status register, shown in figure 2-4, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." figure 2-4: status register (address 03h, 83h) note 1: these devices do not use bits irp and rp1 (status<7:6>). maintain these bits clear to ensure upward compatibility with future products. note 2: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) - not implemented, maintain clear 0 = bank 0, 1 (00h - ffh) - not implemented, maintain clear bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes note: rp1 = not implemented, maintain clear bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c712/716 ds41106a-page 14 preliminary ? 1999 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. figure 2-5: option_reg register (address 81h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 15 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. figure 2-6: intcon register (address 0bh, 8bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: iinte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16c712/716 ds41106a-page 16 preliminary ? 1999 microchip technology inc. 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. figure 2-7: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as 0 bit 6: adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5-3: unimplemented : read as 0 bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 17 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. figure 2-8: pir1 register (address 0ch) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented : read as 0 bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5-3: unimplemented : read as 0 bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow
pic16c712/716 ds41106a-page 18 preliminary ? 1999 microchip technology inc. 2.2.2.6 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. these devices contain an additional bit to differentiate a brown-out reset condition from a power-on reset condition. figure 2-9: pcon register (address 8eh) note: if the boden configuration bit is set, bor is 1 on power-on reset. if the boden configuration bit is clear, bor is unknown on power-on reset. the bor status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the boden configura- tion bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q por bor r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 19 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. 2.3.1 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. midrange devices have an 8 level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modified when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper bit of the address is provided by pclath<3>. when doing a call or goto instruction, the user must ensure that the page select bit is pro- grammed so that the desired program memory page is addressed. if a return from a call instruction (or inter- rupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<3> bit is not required for the return instructions (which pops the address from the stack).
pic16c712/716 ds41106a-page 20 preliminary ? 1999 microchip technology inc. 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 2-1: indirect addressing ? register file 05 contains the value 10h ? register file 06 contains the value 0ah ? load the value 05 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 06) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-10. however, irp is not used in the pic16c712/716. figure 2-10: direct/indirect addressing note 1: for register file map detail see figure 2-3. 2: maintain clear for upward compatibility with future products. 3: not implemented. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h (3) (3) (2) (2)
1998 microchip technology inc. preliminary ds41106a-page 21 pic16c712/716 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual, (ds33023). 3.1 porta and the trisa register porta is a 5-bit wide bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (=0) will make the corresponding porta pin an output, (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore a write to a port implies that the port pins are read, the value is modified, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. porta pins, ra3:0, are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 3-1: initializing porta bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xef ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<4> as outputs bcf status, rp0 ; return to bank 0 note: on a power-on reset, these pins are con- figured as analog inputs and read as '0'. figure 3-1: block diagram of ra3:ra0 data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin analog input mode ttl input buffer to a / d c o n ve r t e r v ss v dd
pic16c712/716 ds41106a-page 22 preliminary 1998 microchip technology inc. figure 3-2: block diagram of ra4/t0cki pin table 3-1 porta functions table 3-2 summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2 bit2 ttl input/output or analog input ra3/an3/v ref bit3 ttl input/output or analog input or v ref ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta (1) ra4 ra3 ra2 ra1 ra0 --xx xxxx --xu uuuu 85h trisa (1) porta data direction register --11 1111 --11 1111 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: reserved bits; do not use. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin tmr0 clock input q d q ck q d q ck en qd en v ss
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 23 3.2 portb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (=0) will make the corresponding portb pin an output, (i.e., put the contents of the output latch on the selected pin). example 3-1: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 3-3: block diagram of rb0 pin data latch rbpu (1) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin ttl input buffer schmitt trigger buffer tris latch note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). v ss v dd
pic16c712/716 ds41106a-page 24 preliminary ? 1999 microchip technology inc. portb pins rb3:rb1 are multiplexed with several peripheral functions (table 3-3). portb pins rb3:rb0 have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portb pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisb as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- figured as an output is excluded from the interrupt on change comparison). the input pins, rb7:rb4, are compared with the old value latched on the last read of portb. the mismatch outputs of rb7:rb4 are ored together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb will end the mis- match condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 3-4: block diagram of rb1/t1oso/t1cki pin 0 1 q d q ck q d q ck q d q ck q d q ck 0 1 0 1 ttl buffer trisb<1> portb<1> trisccp<0> dataccp<0> rb1/t1oso/t1cki rd data bus wr wr wr wr trisb t1oscen rd portb tmr1cs dataccp dataccp trisccp portb t1clkin st buffer p v dd weak pull-up rbpu ( 1 ) t1oscen t1cs v ss v dd note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 25 figure 3-5: block diagram of rb2/t1osi pin figure 3-6: block diagram of rb3/ccp1 pin p v dd weak pull-up q d q ck q d q ck ttl buffer trisb<2> portb<2> data bus wr portb wr trisb t1oscen rd portb rb1/t1oso/t1cki rbpu ( 1 ) t1oscen v ss v dd note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). 0 1 q d q ck q d q ck q d q ck q d q ck 0 1 0 1 trisb<3> portb<3> trisccp<2> dataccp<2> rb3/ccp1 rd data bus wr wr wr wr rd portb ccpon ttl buffer 0 1 0 1 ccpout ccpin ccpon dataccp dataccp trisccp portb trisb ccp output mode p v dd weak pull-up rbpu ( 1 ) ccpon v ss v dd note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c712/716 ds41106a-page 26 preliminary ? 1999 microchip technology inc. figure 3-7: block diagram of rb7:rb4 pins table 3-3 portb functions name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1/t1os0/ t1cki bit1 ttl/st (1) input/output pin or timer 1 oscillator output, or timer 1 clock input. internal software programmable weak pull-up. see timer1 section for detailed operation. rb2/t1osi bit2 ttl/st (1) input/output pin or timer 1 oscillator input. internal software programmable weak pull-up. see timer1 section for detailed operation. rb3/ccp1 bit3 ttl/st (1) input/output pin or capture 1 input, or compare 1 output, or pwm1 output. internal software programmable weak pull-up. see ccp1 section for detailed operation. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt or peripheral input. 2: this buffer is a schmitt trigger input when used in serial programming mode. data latch from other rbpu (1) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl buffer pin st buffer rb7:rb6 in serial programming mode q3 q1 note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). v ss v dd
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 27 table 3-4 summary of registers associated with portb address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb portb data direction register 1111 1111 1111 1111 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c712/716 ds41106a-page 28 preliminary ? 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 29 4.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter ? readable and writable ? internal or external clock select ? edge select for external clock ? 8-bit software programmable prescaler ? interrupt on overflow from ffh to 00h figure 4-1 is a simplified block diagram of the timer0 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 4.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. additional information on external clock requirements is available in the picmicro? mid-range reference manual, (ds33023). 4.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer, respectively (figure 4-2). for simplicity, this counter is being referred to as prescaler throughout this data sheet. note that there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer and vice-versa. the prescaler is not readable or writable. the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 4-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 4-2 for detailed block diagram). ra4/t0cki t0se ( 1 ) 0 1 1 0 pin t0cs ( 1 ) f osc /4 programmable prescaler ( 2 ) sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ( 1 ) ps2, ps1, ps0 ( 1 ) set interrupt flag bit t0if on overflow 3
pic16c712/716 ds41106a-page 30 preliminary ? 1999 microchip technology inc. 4.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed on the fly during program execution. 4.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 4-2: block diagram of the timer0/wdt prescaler table 4-1 registers associated with timer0 note: to avoid an unintended device reset, a specific instruction sequence (shown in the picmicro? mid-range reference manual, ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is dis- abled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa (1) bit 4 porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. note 1: reserved bit; do not use. ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 31 5.0 timer1 module the timer1 module timer/counter has the following fea- tures: ? 16-bit timer/counter (two 8-bit registers; tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt on overflow from ffffh to 0000h ? reset from ccp module trigger timer1 has a control register, shown in figure 5-1. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 5-2 is a simplified block diagram of the timer1 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 5.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rb2/t1osi and rb1/t1oso/t1cki pins become inputs. that is, the trisb<2:1> value is ignored. timer1 also has an internal reset input. this reset can be generated by the ccp module (section 7.0). figure 5-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rb1/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c712/716 ds41106a-page 32 preliminary ? 1999 microchip technology inc. figure 5-2: timer1 block diagram 5.2 timer1 module and portb operation when timer1 is configured as timer running from the main oscillator, portb<2:1> operate as normal i/o lines. when timer1 is configured to function as a counter however, the clock source selection may affect the operation of portb<2:1>. multiplexing details of the timer1 clock selection on portb are shown in fig- ure 3-4 and figure 3-5. the clock source for timer1 in the counter mode can be from one of the following: 1. external circuit connected to the rb1/t1oso/t1cki pin 2. firmware controlled dataccp<0> bit, dt1cki 3. timer1 oscillator table 5-1 shows the details of timer1 mode selections, control bit settings, tmr1 and portb operations. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rb1/t1oso/t1cki rb2/t1osi note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 33 table 5-1 tmr1 module and portb operation tmr1 module mode clock source control bits tmr1 module operation portb<2:1> operation off n/a t1con = --xx 0x00 off portb<2:1> function as normal i/o timer fosc/4 t1con = --xx 0x01 tmr1 module uses the main oscillator as clock source. tmr1on can turn on or turn off timer1. portb<2:1> function as normal i/o counter external circuit t1con = --xx 0x11 tr1sccp = ---- -x-1 tmr1 module uses the external signal on the rb1/t1oso/t1cki pin as a clock source. tmr1on can turn on or turn off timer1. dt1ck can read the signal on the rb1/t1oso/t1cki pin. portb<2> functions as normal i/o. portb<1> always reads 0 when configured as input . if portb<1> is configured as out- put, reading portb<1> will read the data latch. writing to portb<1> will always store the result in the data latch, but not to the rb1/t1oso/t1cki pin. if the tmr1cs bit is cleared (tmr1 reverts to the timer mode), then pin portb<1> will be driven with the value in the data latch. firmware t1con = --xx 0x11 tr1sccp = ---- -x-0 dataccp<0> bit drives rb1/t1oso/t1cki and pro- duces the tmr1 clock source. tmr1on can turn on or turn off timer1. the dataccp<0> bit, dt1ck, can read and write to the rb1/t1oso/t1cki pin. timer1 oscillator t1con = --xx 1x11 rb1/t1oso/t1cki and rb2/t1osi are configured as a 2 pin crystal oscillator. rb1/t1osi/t1cki is the clock input for tmr1. tmr1on can turn on or turn off timer1. dataccp<1> bit, dt1ck, always reads 0 as input and can not write to the rb1/t1oso/t1ck1 pin. portb<2:1> always read 0 when configured as inputs. if portb<2:1> are configured as outputs, reading portb<2:1> will read the data latches. writing to portb<2:1> will always store the result in the data latches, but not to the rb2/t1osi and rb1/t1oso/t1cki pins. if the tmr1cs and t1oscen bits are cleared (tmr1 reverts to the timer mode and tmr1 oscillator is disabled), then pin portb<2:1> will be driven with the value in the data latches.
pic16c712/716 ds41106a-page 34 preliminary ? 1999 microchip technology inc. 5.3 timer1 oscillator a crystal oscillator circuit is built in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 5-2 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 5-2 capacitor selection for the timer1 oscillator 5.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing tmr1 interrupt enable bit tmr1ie (pie1<0>). 5.5 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. table 5-3 registers associated with timer1 as a timer/counter osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -0-- -000 -0-- -000 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 -0-- -000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 07h dataccp dccp dt1ck ---- -x-x ---- -u-u 87h trisccp tccp tt1ck ---- -1-1 ---- -1-1 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 35 notes:
pic16c712/716 ds41106a-page 36 preliminary ? 1999 microchip technology inc. 6.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 timer2 has a control register, shown in figure 6-1. timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 6-2 is a simplified block diagram of the timer2 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). figure 6-1: t2con: timer2 control register (address 12h) figure 6-2: timer2 block diagram u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 0011 = 1:4 postscale 0100 = 1:5 postscale 0101 = 1:6 postscale 0110 = 1:7 postscale 0111 = 1:8 postscale 1000 = 1:9 postscale 1001 = 1:10 postscale 1010 = 1:11 postscale 1011 = 1:12 postscale 1100 = 1:13 postscale 1101 = 1:14 postscale 1110 = 1:15 postscale 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 comparator tmr2 sets flag tmr2 reg output reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if to
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 37 6.1 timer2 operation timer2 can be used as the pwm time-base for pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. 6.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. table 6-1 registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -00- -000 0000 -000 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 0000 -000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module.
pic16c712/716 ds41106a-page 38 preliminary ? 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 39 7.0 capture/compare/pwm (ccp) module(s) each ccp (capture/compare/pwm) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm master/slave duty cycle register. table 7-1 shows the timer resources of the ccp module modes. capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. additional information on the ccp module is available in the picmicro? mid-range reference manual, (ds33023). table 7-1 ccp mode - timer resource figure 7-1: ccp1con register (address 17h) figure 7-2: trisccp register (address 87h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: dc1b1:dc1b0 : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0: ccp1m3:ccp1m0 : ccp1 mode select bits 0000 = capture/compare/pwm off (resets ccp1 module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; ccp1 resets tmr1 and starts an a/d conversion (if a/d module is enabled)) 11xx = pwm mode r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tccptt1ckr =readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7-3: reserved bits; do not use bit 2: tccp - tri state control bit for ccp 0 = output pin driven 1 = output pin tristated bit 1: reserved bit; do not use bit 0: tt1ck - tri state control bit for t1cki pin 0 = t1cki pin is an output 1 = t1cki pin is an input
pic16c712/716 ds41106a-page 40 preliminary ? 1999 microchip technology inc. 7.1 c apture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rb3/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. figure 7-3: capture mode operation block diagram 7.1.1 ccp pin configuration in capture mode, the ccp output must be disabled by setting the trisccp<2> bit. 7.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 7.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 7.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. example 7-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 7-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rb3/ccp1 is configured as an output by clearing the trisccp<2> bit, a write to the dccp bit can cause a capture condi- tion. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rb3/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 41 7.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rb3/ccp1 pin is either: ?driven high ? driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 7-4: compare mode operation block diagram 7.2.1 ccp pin configuration the user must configure the rb3/ccp1 pin as the ccp output by clearing the trisccp<2> bit. 7.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 7.2.3 software interrupt mode when generate software interrupt is chosen the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 7.2.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp1 also starts an a/d conversion (if the a/d module is enabled). table 7-2 registers associated with capture, compare, and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rb3/ccp1 trisccp<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>) which starts an a/d conversion note: clearing the ccp1con register will force the rb3/ccp1 compare output latch to the default low level. this is neither the portb i/o data latch nor the dataccp latch. note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 07h dataccp dccp tt1ck xxxx xxxx xxxx xuxu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -0-- -000 -0-- -000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 87h trisccp tccp tt1ck xxxx x1x1 xxxx x1x1 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 -0-- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1.
pic16c712/716 ds41106a-page 42 preliminary ? 1999 microchip technology inc. 7.3 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portb data latch, the trisccp<2> bit must be cleared to make the ccp1 pin an output. figure 7-5 shows a simplified block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 7.3.3. figure 7-5: simplified pwm block diagram a pwm output (figure 7-6) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 7-6: pwm output 7.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 7.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? tosc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: for an example pwm period and duty cycle calcula- tion, see the picmicro? mid-range reference manual, (ds33023). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is neither the portb i/o data latch nor the dataccp latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisccp<2> rb3/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period = pr2+1 duty cycle tmr2 = pr2 tmr2 = duty cycle (ccpr1h) tmr2 = pr2 note: the timer2 postscaler (see section 6.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits =
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 43 7.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisccp<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 7-3 example pwm frequencies and resolutions at 20 mhz table 7-4 registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 07h dataccp dccp dt1ck xxxx xxxx xxxx xuxu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -0-- -000 -0-- -000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 87h trisccp tccp tt1ck xxxx x1x1 xxxx x1x1 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 -0-- -000 92h pr2 timer2 modules period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2.
pic16c712/716 ds41106a-page 44 preliminary ? 1999 microchip technology inc. 7.4 ccp1 module and portb operation when the ccp module is disabled, portb<3> oper- ates as a normal i/o pin. when the ccp module is enabled, portb<3> operation is affected. multiplex- ing details of the ccp1 module are shown on portb<3>, refer to figure 3.6. table 7-5 below shows the effects of the ccp module operation on portb<3> . table 7-5 ccp1 module and portb operation ccp1 module mode control bits ccp1 module operation portb<3> operation off ccp1con = --xx 0000 off portb<3> functions as normal i/o. capture ccp1con = --xx 01xx tr1sccp = ---- -1-x the ccp1 module will capture an event on the rb3/ccp1 pin which is driven by an external circuit. the dccp bit can read the signal on the rb3/ccp1 pin. portb<3> always reads 0 when config- ured as input. if portb<3> is config- ured as output, reading portb<3> will read the data latch. writing to portb<3> will always store the result in the data latch, but it does not drive the rb3/ccp1 pin. ccp1con = --xx 01xx tr1sccp = ---- -0-x the ccp1 module will capture an event on the rb3/ccp1 pin which is driven by the dccp bit. the dccp bit can read the signal on the rb3/ccp1 pin. compare ccp1con = --xx 10xx tr1sccp = ---- -0-x the ccp1 module produces an output on the rb3/ccp1 pin when a compare event occurs. the dccp bit can read the signal on the rb3/ccp1 pin. pwm ccp1con = --xx 11xx tr1sccp = ---- -0-x the ccp1 module produces the pwm signal on the rb3/ccp1 pin. the dccp bit can read the signal on the rb3/ccp1 pin.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 45 8.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has four inputs. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to applica- tion note an546 for use of a/d converter). the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog reference voltage is software select- able to either the devices positive supply voltage (v dd ) or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. additional information on the a/d module is available in the picmicro? mid-range reference manual, (ds33023). the a/d module has three registers. these registers are: ? a/d result register (adres) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the adcon0 register, shown in figure 8-1, controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 8-2, configures the functions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference) or as dig- ital i/o. figure 8-1: adcon0 register (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal adc rc oscillator) bit 5-3: chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 1xx = reserved, do not use bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conver- sion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic16c712/716 ds41106a-page 46 preliminary ? 1999 microchip technology inc. figure 8-2: adcon1 register (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg2:pcfg0 : a/d port configuration control bits a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra3 v ref 0x0 aaaa v dd 0x1 aaav ref ra3 100 aada v dd 101 aadv ref ra3 11x dddd v dd
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 47 the adres register contains the result of the a/d con- version. when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared and the a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 8-3. the value that is in the adres register is not modified for a power-on reset. the adres register will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 8.1. after this acquisition time has elapsed, the a/d conver- sion can be started. the following steps should be fol- lowed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins/voltage reference/ and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for the next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 8-3: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 110 or 111 001 or 011 or 101 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 011 010 001 000 a/d converter 100 or
pic16c712/716 ds41106a-page 48 preliminary ? 1999 microchip technology inc. 8.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 8-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 10 k w . after the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, t acq , see the picmicro? mid-range reference manual, (ds33023). this equation calculates the acquisition time to within 1/2 lsb error (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified accuracy. figure 8-4: analog input model note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 49 8.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.5t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?2t osc ?8t osc ?32t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. table 8-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 8.3 configuring analog port pins the adcon1 and trisa registers control the opera- tion of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 8-1 t ad vs. device operating frequencies note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs, will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is defined as a digital input (including the an3:an0 pins), may cause the input buffer to con- sume current that is out of the devices specification. ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s6.4 m s 24 m s (3) 32t osc 10 1.6 m s6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when device frequency is greater than 1 mhz, the rc a/d conversion clock source is recommended for sleep operation only. 5: for extended voltage devices (lc), please refer to electrical specifications section.
pic16c712/716 ds41106a-page 50 preliminary ? 1999 microchip technology inc. 8.4 a/d conversions 8.5 use of the ccp trigger an a/d conversion can be started by the special event trigger of the ccp1 module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the special event trigger will be ignored by the a/d module, but will still reset the timer1 counter. table 8-2 summary of a/d registers note: the go/done bit should not be set in the same instruction that turns on the a/d. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta (1) ra4 ra3 ra2 ra1 ra0 --xx xxxx --xu uuuu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif ccp1if tmr2if tmr1if -0-- -000 -0-- -000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 85h trisa (1) porta data direction register ---1 1111 ---1 1111 8ch pie1 adie ccp1ie tmr2ie tmr1ie -0-- -000 -0-- 0000 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: reserved bits; do not use.
1999 microchip technology inc. preliminary ds41106a-page 51 pic16c712/716 9.0 special features of the cpu the pic16c712/716 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. these are: ? osc selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? (icsp) these devices have a watchdog timer, which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay on power-up only and is designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options. additional information on special features is available in the picmicro? mid-range reference manual, (ds33023). 9.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h - 3fffh), which can be accessed only during program- ming.
pic16c712/716 ds41106a-page 52 preliminary 1999 microchip technology inc. figure 9-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 bodencp1 cp0 pwrte wdte fosc1 fosc0 register:config address2007h bit13 bit0 bit 13-8, 5-4: cp1:cp0 : code protection bits (2) code protection for 2k program memory (pic16c716) 11 = programming code protection off 10 = 0400h - 07ffh code protected 01 = 0200h - 07ffh code protected 00 = 0000h - 07ffh code protected bit 13-8, 5-4: code protection for 1k program memory (pic16c712) 11 = programming code protection off 10 = programming code protection off 01 = 0200h - 03ffh code protected 00 = 0000h - 03ffh code protected bit 7: unimplemented : read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regardless of the value of bit pwrte . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1 :cp0 pairs have to be given the same value to enable the code protection scheme listed.
1999 microchip technology inc. preliminary ds41106a-page 53 pic16c712/716 9.2 oscillator configurations 9.2.1 oscillator types the pic16cxxx can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 9.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 9-2). the pic16cxxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/clkin pin (figure 9-3). figure 9-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 9-3: external clock input operation (hs, xt or lp osc configuration) note 1: see table 9-1 and table 9-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16c7xx rs (2) internal osc1 osc2 open clock from ext. system pic16c7xx table 9-1 ceramic resonators table 9-2 capacitor selection for crystal oscillator ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. note 1: recommended values of c1 and c2 are identical to the ranges tested (table 9-1). 2: higher capacitance increases the stability of the oscillator, but also increases the start- up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: rs may be required in hs mode, as well as xt mode to avoid overdriving crystals with low drive level specification.
pic16c712/716 ds41106a-page 54 preliminary 1999 microchip technology inc. 9.2.3 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 9-4 shows how the r/c combina- tion is connected to the pic16cxxx. figure 9-4: rc oscillator mode osc2/clkout cext rext pic16c7xx osc1 fosc/4 internal clock v dd v ss recommended values: 3 k w rext 100 k w cext > 20pf 9.3 reset the pic16cxxx differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) ? brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a reset state on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep and brown-out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situations as indi- cated in table 9-4. these bits are used in software to determine the nature of the reset. see table 9-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 9-6. the picmicro microcontrollers have a mclr noise fil- ter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low.
1999 microchip technology inc. preliminary ds41106a-page 55 pic16c712/716 9.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (to a level of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified (parameter d004). for a slow rise time, see figure 9-5. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure oper- ation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the start-up con- ditions. figure 9-5: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical specification. 3: r1 = 100 w to 1 k w will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r v dd mclr pic16c7xx v dd 9.5 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33), on power-up only, from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/dis- able the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature, and process variation. see dc parameters for details. 9.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and stabi- lized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 9.7 brown-out reset (bo d) the pic16c712/716 members have on-chip brown-out reset circuitry. a configuration bit, boden, can disable (if clear/programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below 4.0v, refer to v bor parameter d005(v bor ) for a time greater than param- eter (t bor ) in table 12-6. the brown-out situation will reset the chip. a reset is not guaranteed to occur if v dd falls below 4.0v for less than parameter (t bor ). on any reset (power-on, brown-out, watchdog, etc.) the chip will remain in reset until v dd rises above v bor . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will execute a 72 ms reset. the power-up timer should always be enabled when brown-out reset is enabled. figure 9-7 shows typical brown-out situations. for operations where the desired brown-out voltage is other than 4v, an external brown-out circuit must be used. figure 9-8, 9-9 and 9-10 show examples of exter- nal brown-out protection circuits.
pic16c712/716 ds41106a-page 56 preliminary 1999 microchip technology inc. figure 9-6: simplified block diagram of on-chip reset circuit figure 9-7: brown-out situations s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1) pwrt boden see table 9-3 for time-out situations. 72 ms v bor v dd internal reset v bor v dd internal reset 72 ms <72 ms 72 ms v bor v dd internal reset
1999 microchip technology inc. preliminary ds41106a-page 57 pic16c712/716 figure 9-8: external brown-out protection circuit 1 figure 9-9: external brown-out protection circuit 2 note 1: this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. 2: internal brown-out reset circuitry should be disabled when using this cir- cuit. v dd 33k 10k 40k v dd mclr pic16c7xx q1 note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out reset should be dis- abled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd x r1 r1 + r2 = 0.7 v v dd r2 40k v dd mclr pic16c7xx r1 q1 figure 9-10: external brown-out protection circuit 3 9.8 time-out sequence on power-up the time-out sequence is as follows: first pwrt time-out is invoked after the por time delay has expired. then ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 9-11, figure 9-12, and figure 9-13 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (figure 9-13). this is useful for testing purposes or to synchronize more than one pic16cxxx device operat- ing in parallel. table 9-5 shows the reset conditions for some special function registers, while table 9-6 shows the reset con- ditions for all the registers. 9.9 power control/status register (pcon) the power control/status register, pcon has two bits. bit0 is brown-out reset status bit, bor . if the boden configuration bit is set, bor is 1 on power-on reset. if the boden configuration bit is clear, bor is unknown on power-on reset. the bor status bit is a "don't care" and is not neces- sarily predictable if the brown-out circuit is disabled (the boden configuration bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. this brown-out protection circuit employs microchip technologys mcp809 microcontroller supervisor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collector outputs with both high and low active reset pins. there are 7 different trip point selections to accommodate 5v and 3v systems mclr pic16c7xx v dd v dd vss rst mcp809 v dd bypass capacitor
pic16c712/716 ds41106a-page 58 preliminary 1999 microchip technology inc. table 9-3 time-out in various situations table 9-4 status bits and their significance table 9-5 reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
1999 microchip technology inc. preliminary ds41106a-page 59 pic16c712/716 table 9-6 initialization conditions for all registers of the pic16c712/716 register power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta (4) --0x 0000 --xx xxxx --xu uuuu portb (5) xxxx xxxx uuuu uuuu uuuu uuuu dataccp ---- -x-x ---- -u-u ---- -u-u pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 -00x 0000 -00u uuuu -uuu (1) pir1 ---- 0000 ---- 0000 ---- uuuu (1) -0-- 0000 -0-- 0000 -u-- uuuu (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option_reg 1111 1111 1111 1111 uuuu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisccp xxxx x1x1 xxxx x1x1 xxxx xuxu pie1 ---- 0000 ---- 0000 ---- uuuu -0-- 0000 -0-- 0000 -u-- uuuu pcon ---- --0q ---- --uq ---- --uq pr2 1111 1111 1111 1111 1111 1111 adcon1 ---- -000 ---- -000 ---- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 9-5 for reset value for specific condition. 4: on any device reset, these pins are configured as inputs. 5: this is the value that will be in the port output latch.
pic16c712/716 ds41106a-page 60 preliminary 1999 microchip technology inc. figure 9-11: time-out sequence on power-up (mclr tied to v dd ) figure 9-12: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 9-13: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
1999 microchip technology inc. preliminary ds41106a-page 61 pic16c712/716 9.10 interrupts the pic16c712/716 devices have up to 7 sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. the peripheral interrupt flags are contained in the spe- cial function registers, pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers, pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister, intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. figure 9-14: interrupt logic adif adie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu
pic16c712/716 ds41106a-page 62 preliminary 1999 microchip technology inc. 9.10.1 int interrupt external interrupt on rb0/int pin is edge triggered, either rising if bit intedg (option_reg<6>) is set, or falling if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 9.13 for details on sleep mode. 9.10.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 4.0) 9.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 3.2) 9.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt, (i.e., w register and status register). this will have to be implemented in software. example 9-1 stores and restores the w and status registers. the register, w_temp, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register. d) executes the interrupt service routine code (user-generated). e) restores the status register (and bank select bit). f) restores the w and pclath registers. example 9-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page bcf status, irp ;return to bank 0 movf fsr, w ;copy fsr to w movwf fsr_temp ;copy fsr from w to fsr_temp : :(isr) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
1999 microchip technology inc. preliminary ds41106a-page 63 pic16c712/716 9.12 watchdog timer (wdt) the watchdog timer is as a free running, on-chip, rc oscillator which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device have been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdte (section 9.1). wdt time-out period values may be found in the elec- trical specifications section under t wdt (parameter #31). values for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler) may be assigned using the option_reg register. . note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. figure 9-15: watchdog timer block diagram figure 9-16: summary of watchdog timer registers address name bits 13:8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h option_reg n/a rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 9-1 for operation of these bits. from tmr0 clock source (figure 4-2) to tmr0 (figure 4-2) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8
pic16c712/716 ds41106a-page 64 preliminary 1999 microchip technology inc. 9.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and the disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 9.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 9.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
1999 microchip technology inc. preliminary ds41106a-page 65 pic16c712/716 figure 9-17: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will cont inue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. 9.14 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 9.15 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. for rom devices, these values are submitted along with the rom code. note: microchip does not recommend code pro- tecting windowed devices. 9.16 in-circuit serial programming ? pic16cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming volt- age. this allows customers to manufacture boards with unprogrammed devices, and then program the micro- controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. for complete details on serial programming, please refer to the in-circuit serial programming (icsp?) guide, (ds30277).
pic16c712/716 ds41106a-page 66 preliminary 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 67 10.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxxx instruc- tion set summary in table 10-2 lists byte-oriented , bit- oriented , and literal and control operations. table 10- 1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 10-1 opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 10-2 lists the instructions recognized by the mpasm assembler. figure 10-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 10-1: general format for instructions a description of each instruction is available in the picmicro? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit z zero bit dc digit carry bit c carry bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c712/716 ds41106a-page 68 preliminary ? 1999 microchip technology inc. table 10-2 pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
? 1999 microchip technology inc. preliminary ds41106a-page 69 pic16c712/716 11.0 development support 11.1 development tools the picmicro a microcontrollers are supported with a full range of hardware and software development tools: ? mplab ? -ice real-time in-circuit emulator ? icepic ? low-cost pic16c5x and pic16cxxx in-circuit emulator ?pro mate a ii universal programmer ? picstart a plus entry-level prototype programmer ? simice ? picdem-1 low-cost demonstration board ? picdem-2 low-cost demonstration board ? picdem-3 low-cost demonstration board ? mpasm assembler ? mplab ? sim software simulator ? mplab-c17 (c compiler) ? fuzzy logic development system ( fuzzy tech a - mp) ?k ee l oq ? evaluation kits and programmer 11.2 mplab-ice: high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). mplab-ice is sup- plied with the mplab integrated development environ- ment (ide), which allows editing, make and download, and source debugging from a single envi- ronment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support all new microchip micro- controllers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x or windows 95 environment were chosen to best make these features available to you, the end user. mplab-ice is available in two versions. mplab-ice 1000 is a basic, low-cost emulator system with simple trace capabilities. it shares processor mod- ules with the mplab-ice 2000. this is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. both systems will operate across the entire operating speed range of the picmicro mcu. 11.3 icepic: low-cost picmicro in-circuit emulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 386 through pentium ? based machines under windows 3.x, windows 95, or win- dows nt environment. icepic features real time, non- intrusive emulation. 11.4 pro mate ii: universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set configuration and code-protect bits in this mode. 11.5 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923, pic16c924 and pic17c756 may be sup- ported with an adapter socket. picstart plus is ce compliant.
pic16c712/716 ds41106a-page 70 preliminary ? 1999 microchip technology inc. 11.6 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab?-sim. both sim- ice and mplab-sim run under microchip technol- ogys mplab integrated development environment (ide) software. specifically, simice provides hardware simulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrol- lers. simice works in conjunction with mplab-sim to provide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valuable debugging tool for entry- level system development. 11.7 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 11.8 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 11.9 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
? 1999 microchip technology inc. preliminary ds41106a-page 71 pic16c712/716 11.10 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: ? a full featured editor ? three operating modes -editor -emulator - simulator ? a project manager ? customizable tool bar and key mapping ? a status bar with project information ? extensive on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 11.11 assembler (mpasm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from mplab- ice, microchips universal emulator system. mpasm has the following features to assist in develop- ing software for specific use applications. ? provides translation of assembler source code to object code for all microchip microcontrollers. ? macro assembly capability. ? produces all the files (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. ? supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro. directives are helpful in making the development of your assemble source code shorter and more maintainable. 11.12 software simulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the picmicro series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mpasm. the software simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 11.13 mplab-c17 compiler the mplab-c17 code development system is a complete ansi c compiler and integrated develop- ment environment for microchips pic17cxxx family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 11.14 fuzzy logic development system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 11.15 seeval a evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system.
pic16c712/716 ds41106a-page 72 preliminary ? 1999 microchip technology inc. 11.16 k ee l oq a evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1999 microchip technology inc. preliminary ds41106a-page 73 pic16c712/716 table 11-1 development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab ?-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model programmer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq ? evaluation kit k ee l oq transponder kit
pic16c712/716 ds41106a-page 74 preliminary ? 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 75 12.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... .-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr , and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2).......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1)(pdip and soic) ................................................................................ ....................1.0w total power dissipation (note 1)(ssop) ......................................................................................... ........................0.65w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta and portb (combined) .................................................................................200 ma maximum current sourced by porta and portb (combined).......................................................................... ..200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a low level to the mclr /v pp pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c712/716 ds41106a-page 76 preliminary ? 1999 microchip technology inc. figure 12-1: pic16c712/716 voltage-frequency graph, -40c < ta < +125c figure 12-2: pic16lc712/716 voltage-frequency graph, 0c < ta < +70c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 4 10 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 77 12.1 dc characteristics: pic16c712/716-04 (commercial, industrial, extended) pic16c712/716-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 v bor * - - 5.5 5.5 v v bor enabled (note 7) d002* v dr ram data retention voltage (1) -1.5- v d003 v por v dd start voltage to ensure inter- nal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d013 i dd supply current (2,5) - - 0.8 4.0 2.5 8.0 ma ma f osc = 4 mhz, v dd = 4.0v f osc = 20 mhz, v dd = 4.0v d020 d021 d021b i pd power-down current (3,5) - - - - 10.5 1.5 1.5 2.5 42 16 19 19 m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled, 0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-40 c to +125 c d022* d022a* d i wdt d i bor module differential current (6) watchdog timer brown-out reset - - 6.0 tbd 20 200 m a m a wdte bit set, v dd = 4.0v boden bit set, v dd = 5.0v 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: this is the voltage where the device enters the brown-out reset. when bor is enabled, the device will operate correctly to this trip point.
pic16c712/716 ds41106a-page 78 preliminary ? 1999 microchip technology inc. 12.2 dc characteristics: pic16lc712/716-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 v bor * - - 5.5 5.5 v v bor enabled (note 7) d002* v dr ram data retention voltage (1) -1.5- v d003 v por v dd start voltage to ensure inter- nal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d010a i dd supply current (2,5) - - 2.0 22.5 3.8 48 ma m a xt, rc osc modes f osc = 4 mhz, v dd = 3.0v (note 4) lp osc mode f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a i pd power-down current (3,5) - - - 7.5 0.9 0.9 30 5 5 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c d022* d022a* d i wdt d i bor module differential current (6) watchdog timer brown-out reset - - 6.0 tbd 20 200 m a m a wdte bit set, v dd = 4.0v boden bit set, v dd = 5.0v 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: this is the voltage where the device enters the brown-out reset. when bor is enabled, the device will operate correctly to this trip point.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 79 12.3 dc characteristics: pic16c712/716-04 (commercial, industrial, extended) pic16c712716-20 (commercial, industrial, extended) pic16lc712/716-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 12.1 and section 12.2 param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 d030a with ttl buffer v ss v ss - - 0.8v 0.15v dd v v 4.5v v dd 5.5v otherwise d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp modes) vss - 0.3v dd vnote1 input high voltage v ih i/o ports - d040 with ttl buffer 2.0 - v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd votherwise d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp modes) 0.7v dd -v dd vnote1 d043 osc1 (in rc mode) 0.9v dd -v dd v input leakage current (notes 2, 3) d060 i il i/o ports - - 1 m avss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki - - 5 m avss v pin v dd d063 osc1 - - 5 m avss v pin v dd , xt, hs and lp osc modes d070 i purb portb weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss output low voltage d080 v ol i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c --0.6vi ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc mode) --0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c --0.6vi ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmi- cro be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is defined as current sourced by the pin.
pic16c712/716 ds41106a-page 80 preliminary ? 1999 microchip technology inc. output high voltage d090 v oh i/o ports (note 3) v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc mode) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open-drain high voltage - - 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) --50pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 12.1 and section 12.2 param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmi- cro be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is defined as current sourced by the pin.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 81 12.4 ac (timing) characteristics 12.4.1 timing parameter symbology the timing parameter symbols have been created using one of the following formats: 1. tpps2pps 2. tpps t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance
pic16c712/716 ds41106a-page 82 preliminary ? 1999 microchip technology inc. 12.4.2 timing conditions the temperature and voltages specified in table 12-1 apply to all timing specifications, unless otherwise noted. figure 12-1 specifies the load conditions for the timing specifications. table 12-1 temperature and voltage specifications - ac figure 12-1: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 12.1 and section 12.2. lc parts operate for commercial/industrial temps only. v dd /2 c l r l pin pin v ss v ss c l r l =464 w c l = 50 pf for all pins except osc2/clkout 15 pf for osc2 output load condition 1 load condition 2
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 83 12.4.3 timing diagrams and specifications figure 12-2: external clock timing table 12-2 external clock timing requirements param no. sym characteristic min typ? max units conditions 1a f osc external clkin frequency (note 1) dc 4 mhz rc and xt osc modes dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1t osc external clkin period (note 1) 250 ns rc and xt osc modes 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc 3* tosl, to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c712/716 ds41106a-page 84 preliminary ? 1999 microchip technology inc. figure 12-3: clkout and i/o timing table 12-3 clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) standard 100 ns 18a* extended (lc) 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time standard 10 40 ns 20a* extended (lc) 80 ns 21* tiof port output fall time standard 10 40 ns 21a* extended (lc) 80 ns 22??* t inp int pin high or low time t cy ns 23??* t rbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 12-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 85 figure 12-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 12-5: brown-out reset timing table 12-4 reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40c to +125c 31* t wdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40c to +125c 32 t ost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +125c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 12-1 for load conditions. v dd bv dd 35
pic16c712/716 ds41106a-page 86 preliminary ? 1999 microchip technology inc. figure 12-6: timer0 and timer1 external clock timings table 12-5 timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4,..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard 15 ns extended (lc) 25 ns asynchronous standard 30 ns extended (lc) 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard 15 ns extended (lc) 25 ns asynchronous standard 30 ns extended (lc) 50 ns 47* tt1p t1cki input period synchronous standard greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) extended (lc) greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard 60 ns extended (lc) 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 12-1 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 87 figure 12-7: capture/compare/pwm timings table 12-6 capture/compare/pwm requirements param no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler standard 10 ns extended (lc) 20 ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler standard 10 ns extended (lc) 20 ns 52* tccp ccp1 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 output rise time standard 10 25 ns extended (lc) 25 45 ns 54* tccf ccp1 output fall time standard 10 25 ns extended (lc) 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 12-1 for load conditions. ccp1 (capture mode) 50 51 52 ccp1 53 54 (compare or pwm mode)
pic16c712/716 ds41106a-page 88 preliminary ? 1999 microchip technology inc. table 12-7 a/d converter characteristics: pic16c712/716-04 (commercial, industrial, extended) pic16c712/716-20 (commercial, industrial, extended) pic16lc712/716-04 (commercial, industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution 8-bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaranteed (note 3) v ss v ain v ref a20 v ref reference voltage 2.5v v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd ) standard 180 m a average current consump- tion when a/d is on. (note 1) extended (lc) 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 9.1. during a/d conversion cycle 2: * these parameters are characterized but not tested. 3: ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes.
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 89 figure 12-8: a/d conversion timing table 12-8 a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period standard 1.6 m st osc based, v ref 3 3.0v extended (lc) 2.0 m st osc based, v ref full range standard 2.0 4.0 6.0 m s a/d rc mode extended (lc) 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 11 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minimum time is the amplifier settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert ? sample time 1.5 t ad : * these parameters are characterized but not tested. : ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. : this specification ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 9.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy 134
pic16c712/716 ds41106a-page 90 preliminary ? 1999 microchip technology inc. notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 91 13.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25 c. 'max' or 'min' represents (mean + 3 s ) or (mean - 3 s ) respectively, where s is standard deviation, over the whole temperature range. graphs and tables not available at this time.
pic16c712/716 ds41106a-page 92 preliminary ? 1999 microchip technology inc. notes:
1999 microchip technology inc. preliminary ds41106a-page 93 pic16c712/716 14.0 packaging information 14.1 package marking information 18-lead soic aabbcde example pic16c712 xxxxxxxxxxxxxxxxx aabbcde 18-lead pdip example pic16c716-04/p example 18-lead cerdip windowed xxxxxxxx aabbcde 16c716 aabbcde xxxxxxxxxx xxxxxxxxxx 20-lead ssop -20i/ss025 pic16c712 example legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 9917hat 9917cat 9910/saa 9917sbp * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxx /jw -20/so
pic16c712/716 ds41106a-page 94 preliminary 1999 microchip technology inc. package type: k04-007 18-lead plastic dual in-line (p) C 300 mil * controlling parameter. ? dimension b1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b1. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. jedec equivalent: ms-001 ac units inches* millimeters dimension limits min nom max min nom max pcb row spacing 0.300 7.62 number of pins n 18 18 pitch p 0.100 2.54 lower lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thickness c 0.005 0.010 0.015 0.13 0.25 0.38 top to seating plane a 0.110 0.155 0.155 2.79 3.94 3.94 top of lead to seating plane a1 0.075 0.095 0.115 1.91 2.41 2.92 base to seating plane a2 0.000 0.020 0.020 0.00 0.51 0.51 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 package length d ? 0.890 0.895 0.900 22.61 22.73 22.86 molded package width e ? 0.245 0.255 0.265 6.22 6.48 6.73 radius to radius width e1 0.230 0.250 0.270 5.84 6.35 6.86 overall row spacing eb 0.310 0.349 0.387 7.87 8.85 9.83 mold draft angle top a 5 10 15 5 10 15 mold draft angle bottom b 5 10 15 5 10 15 r n 2 1 d e c eb b e1 a p a1 l b1 b a a2
1999 microchip technology inc. preliminary ds41106a-page 95 pic16c712/716 package type: k04-010 18-lead ceramic dual in-line with window (jw) C 300 mil * controlling parameter. jedec equivalent: mo-036 ae n 2 1 r min window length window width overall row spacing radius to radius width package width package length tip to seating plane base to seating plane top of lead to seating plane top to seating plane lead thickness shoulder radius upper lead width lower lead width number of pins pcb row spacing dimension limits pitch units eb w2 w1 l e e1 d a1 a2 a b c r b1 n p 0.15 7.24 7.87 0.76 3.33 4.83 0.30 0.38 1.52 0.53 2.59 0.200 0.140 0.385 0.270 0.298 0.900 0.138 0.023 0.111 0.183 0.190 0.130 0.345 0.125 0.255 0.285 0.880 0.015 0.091 0.175 0.210 0.150 0.425 0.150 0.285 0.310 0.920 0.030 0.131 0.190 0.010 0.013 0.055 0.019 0.100 0.300 nom 0.016 0.008 0.010 0.050 0.098 inches* max 18 0.021 0.012 0.015 0.060 0.102 22.86 0.19 0.13 8.76 6.48 7.24 22.35 3.18 0.00 2.31 4.45 0.2 0.14 9.78 10.80 0.21 3.49 6.86 7.56 0.57 2.82 4.64 3.81 23.37 nom millimeters min 0.20 0.25 1.27 0.41 2.49 max 0.47 0.25 0.32 1.40 2.54 18 7.62 d w2 e w1 c eb e1 p l a1 b b1 a a2
pic16c712/716 ds41106a-page 96 preliminary 1999 microchip technology inc. package type: k04-051 18-lead plastic small outline (so) C wide, 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 min n number of pins mold draft angle bottom mold draft angle top lower lead width chamfer distance outside dimension molded package width molded package length overall pack. height lead thickness radius centerline foot angle foot length gull wing radius shoulder radius standoff shoulder height b a r2 r1 e1 a2 a1 x f b ? c l1 l e ? d ? a dimension limits pitch units p 18 18 0 0 12 12 15 15 4 0.020 0 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 8 0.419 0.299 0.462 0.011 0.068 0.104 0 0 12 12 15 15 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 48 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 inches* 0.050 nom max 1.27 millimeters min nom max n 2 1 r2 r1 l1 l b c f x 45 d p b e e1 a a1 a2 a * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. jedec equivalent: ms-013 ab
1999 microchip technology inc. preliminary ds41106a-page 97 pic16c712/716 package type: k04-072 20-lead plastic shrink small outine (ss) C 5.30 mm min p pitch mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins b a c f a2 a1 a n e1 b ? l1 r2 l r1 e ? d ? dimension limits units 0.65 0.026 8 0 0 5 510 10 0.012 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.283 0.005 0.036 0.073 20 0.301 0 0.010 0.005 0.000 0.015 0.005 0.005 0.205 0.278 0.002 0.026 0.068 0.311 0.015 0.009 0.010 0.025 0.010 0.010 48 0.212 0.289 0.008 0.046 0.078 0 05 510 10 7.65 0.25 0.13 0.00 0.38 0.13 0.13 0 5.20 7.07 0.05 0.66 1.73 7.90 7.78 4 0.32 0.18 0.13 0.13 0.51 0.13 0.38 0.22 0.25 0.25 0.64 0.25 5.29 7.20 0.13 20 1.86 0.91 5.38 7.33 0.21 1.99 1.17 nom inches max nom millimeters* min max n 1 2 r1 r2 d p b e1 e l1 l c b f a a1 a a2 * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. jedec equivalent: mo-150 ae
1999 microchip technology inc. preliminary ds41106a-page 98 pic16c712/716 notes:
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 99 appendix a: revision history appendix b: conversion considerations there are no previous versions of this device. appendix c: migration from base-line to mid-range devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to a mid-range device (i.e., pic16cxxx). the following are the list of modifications over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. bits pa2, pa1, pa0 are removed from status register. 3. data memory paging is redefined slightly. status register is modified. 4. four new instructions have been added: return, retfie, addlw , and sublw . two instructions tris and option are being phased out although they are kept for compati- bility with pic16c5x. 5. option_reg and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. reg- isters are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. t0cki pin is also a port pin (ra4) now. 14. fsr is made a full eight bit register. 15. in-circuit serial programming is made possible. the user can program pic16cxx devices using only five pins: v dd , v ss , mclr /v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ). 17. code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. brown-out protection circuitry has been added. controlled by configuration word bit boden. brown-out reset ensures the device is placed in a reset condition if v dd dips below a fixed set- point. to convert code written for pic16c5x to pic16cxxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h. version date revision description a 2/99 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c6x data sheet , ds30234, and the pic16c7x data sheet , ds30390.
pic16c712/716 ds41106a-page 100 preliminary ? 1999 microchip technology inc. notes:
1999 microchip technology inc. preliminary ds41106a-page 101 pic16c712/716 index a a/d ..................................................................................... 45 a/d converter enable (adie bit) ............................... 16 a/d converter flag (adif bit) ............................. 17, 47 a/d converter interrupt, configuring ......................... 47 adcon0 register ................................................ 11, 45 adcon1 register .......................................... 12, 45, 46 adres register ............................................ 11, 45, 47 analog port pins, configuring .................................... 49 block diagram ............................................................ 47 block diagram, analog input model ........................... 48 channel select (chs2:chs0 bits) ............................ 45 clock select (adcs1:adcs0 bits) ............................ 45 configuring the module .............................................. 47 conversion clock (t ad ) ............................................. 49 conversion status (go/done bit) ...................... 45, 47 conversions ............................................................... 50 converter characteristics .......................................... 88 module on/off (adon bit) ......................................... 45 port configuration control (pcfg2:pcfg0 bits) ...... 46 sampling requirements ............................................. 48 special event trigger (ccp) ................................ 41, 50 timing diagram .......................................................... 89 absolute maximum ratings ............................................... 75 adcon0 register ........................................................ 11, 45 adcs1:adcs0 bits ................................................... 45 adon bit ................................................................... 45 chs2:chs0 bits ........................................................ 45 go/done bit ....................................................... 45, 47 adcon1 register .................................................. 12, 45, 46 pcfg2:pcfg0 bits ................................................... 46 adres register .................................................... 11, 45, 47 architecture pic16c62b/pic16c72a block diagram ...................... 5 assembler mpasm assembler .................................................... 71 b banking, data memory ................................................ 10, 13 brown-out detect (bod) ................................................... 55 brown-out reset (bor) ................................... 51, 54, 58, 59 bor enable (boden bit) .......................................... 52 bor status (bor bit) ................................................ 18 timing diagram .......................................................... 85 c capture (ccp module) ...................................................... 40 block diagram ............................................................ 40 ccp pin configuration ............................................... 40 ccpr1h:ccpr1l registers ..................................... 40 changing between capture prescalers ..................... 40 software interrupt ...................................................... 40 timer1 mode selection .............................................. 40 capture/compare/pwm (ccp) .......................................... 39 ccp1con register ............................................. 11, 39 ccpr1h register ................................................ 11, 39 ccpr1l register ................................................ 11, 39 enable (ccp1ie bit) .................................................. 16 flag (ccp1if bit) ....................................................... 17 timer resources ........................................................ 39 timing diagram .......................................................... 87 ccp1con register ........................................................... 39 ccp1m3:ccp1m0 bits .............................................. 39 ccp1x:ccp1y bits ................................................... 39 code protection ........................................................... 51, 65 cp1:cp0 bits ............................................................. 52 compare (ccp module) .................................................... 41 block diagram ........................................................... 41 ccp pin configuration .............................................. 41 ccpr1h:ccpr1l registers .................................... 41 software interrupt ...................................................... 41 special event trigger .................................... 34, 41, 50 timer1 mode selection .............................................. 41 configuration bits .............................................................. 51 conversion considerations ................................................ 99 d data memory ..................................................................... 10 bank select (rp1:rp0 bits) ................................ 10, 13 general purpose registers ....................................... 10 register file map ...................................................... 10 special function registers ........................................ 11 dc characteristics ....................................................... 77, 79 development support ........................................................ 69 development tools ............................................................ 69 direct addressing .............................................................. 20 e electrical characteristics ................................................... 75 errata ................................................................................... 3 external power-on reset circuit ........................................ 55 f family of devices pic16c7xx ................................................................. 2 firmware instructions ........................................................ 67 fuzzy logic dev. system ( fuzzy tech -mp) ................... 71 i i/o ports ............................................................................ 21 icepic low-cost pic16cxxx in-circuit emulator ........... 69 id locations ................................................................. 51, 65 in-circuit serial programming (icsp) .......................... 51, 65 indirect addressing ............................................................ 20 fsr register ................................................. 10, 11, 20 indf register ............................................................ 11 instruction format .............................................................. 67 instruction set .................................................................... 67 summary table ......................................................... 68 intcon register ......................................................... 11, 15 gie bit ....................................................................... 15 inte bit ..................................................................... 15 intf bit ..................................................................... 15 peie bit ..................................................................... 15 rbie bit ..................................................................... 15 rbif bit ............................................................... 15, 24 t0ie bit ...................................................................... 15 t0if bit ...................................................................... 15 interrupt sources ......................................................... 51, 61 a/d conversion complete ......................................... 47 block diagram ........................................................... 61 capture complete (ccp) .......................................... 40 compare complete (ccp) ........................................ 41 interrupt on change (rb7:rb4 ) ............................... 24 rb0/int pin, external ............................................... 62 tmr0 overflow .................................................... 30, 62 tmr1 overflow .................................................... 31, 34 tmr2 to pr2 match .................................................. 37 tmr2 to pr2 match (pwm) ................................ 36, 42 interrupts, context saving during ...................................... 62 interrupts, enable bits
pic16c712/716 ds41106a-page 102 preliminary 1999 microchip technology inc. a/d converter enable (adie bit) ............................... 16 ccp1 enable (ccp1ie bit) .................................. 16, 40 global interrupt enable (gie bit) ......................... 15, 61 interrupt on change (rb7:rb4) enable (rbie bit) ................................................. 15, 62 peripheral interrupt enable (peie bit) ....................... 15 rb0/int enable (inte bit) ........................................ 15 tmr0 overflow enable (t0ie bit) .............................. 15 tmr1 overflow enable (tmr1ie bit) ........................ 16 tmr2 to pr2 match enable (tmr2ie bit) ................ 16 interrupts, flag bits a/d converter flag (adif bit) ............................. 17, 47 ccp1 flag (ccp1if bit) ................................ 17, 40, 41 interrupt on change (rb7:rb4) flag (rbif bit) ............................................... 15, 24, 62 rb0/int flag (intf bit) ............................................. 15 tmr0 overflow flag (t0if bit) ............................ 15, 62 tmr1 overflow flag (tmr1if bit) ............................ 17 tmr2 to pr2 match flag (tmr2if bit) ..................... 17 k keeloq evaluation and programming tools ................... 72 m master clear (mclr ) mclr reset, normal operation .................... 54, 58, 59 mclr reset, sleep ..................................... 54, 58, 59 memory organization data memory ............................................................. 10 program memory ......................................................... 9 mplab integrated development environment software ... 71 o opcode field descriptions .............................................. 67 option_reg register ............................................... 12, 14 intedg bit ................................................................ 14 ps2:ps0 bits ....................................................... 14, 29 psa bit ................................................................. 14, 29 rbpu bit .................................................................... 14 t0cs bit ............................................................... 14, 29 t0se bit ............................................................... 14, 29 oscillator configuration ................................................ 51, 53 hs ........................................................................ 53, 58 lp ......................................................................... 53, 58 rc .................................................................. 53, 54, 58 selection (fosc1:fosc0 bits) ................................. 52 xt ........................................................................ 53, 58 oscillator, timer1 ......................................................... 31, 34 oscillator, wdt .................................................................. 63 p packaging .......................................................................... 93 paging, program memory .............................................. 9, 19 pcon register ............................................................ 18, 57 bor bit ...................................................................... 18 por bit ...................................................................... 18 picdem-1 low-cost picmicro demo board ..................... 70 picdem-2 low-cost pic16cxx demo board .................. 70 picdem-3 low-cost pic16cxxx demo board ................ 70 picstart plus entry level development system ........ 69 pie1 register ............................................................... 12, 16 adie bit ..................................................................... 16 ccp1ie bit ................................................................. 16 tmr1ie bit ................................................................. 16 tmr2ie bit ................................................................. 16 pin functions mclr /vpp ................................................................... 6 ra0/an0 ...................................................................... 6 ra1/an1 ...................................................................... 6 ra2/an2 ...................................................................... 6 ra3/an3/vref .............................................................. 6 ra4/t0cki .................................................................. 6 rb0/int ....................................................................... 7 rb1 .............................................................................. 7 rb2 .............................................................................. 7 rb3 .............................................................................. 7 rb4 .............................................................................. 7 rb5 .............................................................................. 7 rb6 .............................................................................. 7 rb7 .............................................................................. 7 vdd .............................................................................. 7 vss ............................................................................... 7 pinout descriptions pic16c62b/pic16c72a .............................................. 6 pir1 register .............................................................. 11, 17 adif bit ..................................................................... 17 ccp1if bit ................................................................. 17 tmr1if bit ................................................................. 17 tmr2if bit ................................................................. 17 pointer, fsr ...................................................................... 20 porta initialization ................................................................ 21 porta register .................................................. 11, 21 ra3:ra0 and ra5 port pins ..................................... 21 ra4/t0cki pin .......................................................... 22 trisa register .................................................... 12, 21 portb initialization ................................................................ 23 portb register .................................................. 11, 23 pull-up enable (rbpu bit) ......................................... 14 rb0/int edge select (intedg bit) .......................... 14 rb0/int pin, external ................................................ 62 rb3:rb0 port pins .................................................... 23 rb7:rb4 interrupt on change ................................... 62 rb7:rb4 interrupt on change enable (rbie bit) 15, 62 rb7:rb4 interrupt on change flag (rbif bit) ............................................... 15, 24, 62 rb7:rb4 port pins .................................................... 26 trisb register .................................................... 12, 23 portc block diagram ..................................................... 24, 25 trisc register .......................................................... 12 postscaler, timer2 select (toutps3:toutps0 bits) ............................ 36 postscaler, wdt ................................................................ 29 assignment (psa bit) .......................................... 14, 29 block diagram ........................................................... 30 rate select (ps2:ps0 bits) ................................. 14, 29 switching between timer0 and wdt ........................ 30 power-on reset (por) .............................. 51, 54, 55, 58, 59 oscillator start-up timer (ost) ........................... 51, 55 por status (por bit) ............................................... 18 power control (pcon) register ................................ 57 power-down (pd bit) ........................................... 13, 54 power-on reset circuit, external ............................... 55 power-up timer (pwrt) ..................................... 51, 55 pwrt enable (pwrte bit) ...................................... 52 time-out (to bit) ................................................. 13, 54 time-out sequence ................................................... 57 time-out sequence on power-up .............................. 60 timing diagram ......................................................... 85
1999 microchip technology inc. preliminary ds41106a-page 103 pic16c712/716 prescaler, capture ............................................................. 40 prescaler, timer0 ............................................................... 29 assignment (psa bit) .......................................... 14, 29 block diagram ............................................................ 30 rate select (ps2:ps0 bits) ................................. 14, 29 switching between timer0 and wdt ........................ 30 prescaler, timer1 ............................................................... 32 select (t1ckps1:t1ckps0 bits) .............................. 31 prescaler, timer2 ............................................................... 42 select (t2ckps1:t2ckps0 bits) .............................. 36 pro mate ii universal programmer ............................. 69 product identification system .......................................... 107 program counter pcl register ........................................................ 11, 19 pclath register .......................................... 11, 19, 62 reset conditions ........................................................ 58 program memory ................................................................. 9 interrupt vector ............................................................ 9 paging .................................................................... 9, 19 program memory map ................................................. 9 reset vector ................................................................ 9 program verification .......................................................... 65 programming, device instructions ..................................... 67 pwm (ccp module) .......................................................... 42 block diagram ............................................................ 42 ccpr1h:ccpr1l registers ..................................... 42 duty cycle .................................................................. 42 example frequencies/resolutions ............................ 43 output diagram .......................................................... 42 period ......................................................................... 42 set-up for pwm operation ........................................ 43 tmr2 to pr2 match ............................................ 36, 42 tmr2 to pr2 match enable (tmr2ie bit) ................ 16 tmr2 to pr2 match flag (tmr2if bit) ..................... 17 q q-clock .............................................................................. 42 r ram. see data memory register file ....................................................................... 10 register file map ............................................................... 10 reset ............................................................................ 51, 54 block diagram ............................................................ 56 reset conditions for all registers ............................. 59 reset conditions for pcon register ......................... 58 reset conditions for program counter ...................... 58 reset conditions for status register ..................... 58 timing diagram .......................................................... 85 revision history ................................................................. 99 s seeval evaluation and programming system .............. 71 sleep ................................................................... 51, 54, 64 software simulator (mplab-sim) ..................................... 71 special features of the cpu ............................................. 51 special function registers ................................................ 11 speed, operating ................................................................. 1 stack .................................................................................. 19 status register .................................................. 11, 13, 62 c bit ........................................................................... 13 dc bit ......................................................................... 13 irp bit ........................................................................ 13 pd bit ................................................................... 13, 54 rp1:rp0 bits ............................................................. 13 to bit ................................................................... 13, 54 z bit ............................................................................ 13 t t1con register .......................................................... 11, 31 t1ckps1:t1ckps0 bits ........................................... 31 t1oscen bit ............................................................ 31 t1sync bit ............................................................... 31 tmr1cs bit ............................................................... 31 tmr1on bit .............................................................. 31 t2con register .......................................................... 11, 36 t2ckps1:t2ckps0 bits ........................................... 36 tmr2on bit .............................................................. 36 toutps3:toutps0 bits ......................................... 36 timer0 ............................................................................... 29 block diagram ........................................................... 29 clock source edge select (t0se bit) ................. 14, 29 clock source select (t0cs bit) .......................... 14, 29 overflow enable (t0ie bit) ........................................ 15 overflow flag (t0if bit) ...................................... 15, 62 overflow interrupt ................................................ 30, 62 timing diagram ......................................................... 86 tmr0 register .......................................................... 11 timer1 ............................................................................... 31 block diagram ........................................................... 32 capacitor selection ................................................... 34 clock source select (tmr1cs bit) ........................... 31 external clock input sync (t1sync bit) ................... 31 module on/off (tmr1on bit) ................................... 31 oscillator .............................................................. 31, 34 oscillator enable (t1oscen bit) .............................. 31 overflow enable (tmr1ie bit) .................................. 16 overflow flag (tmr1if bit) ....................................... 17 overflow interrupt ................................................ 31, 34 special event trigger (ccp) ............................... 34, 41 t1con register .................................................. 11, 31 timing diagram ......................................................... 86 tmr1h register .................................................. 11, 31 tmr1l register .................................................. 11, 31 timer2 block diagram ........................................................... 36 pr2 register ................................................. 12, 36, 42 t2con register .................................................. 11, 36 tmr2 register .................................................... 11, 36 tmr2 to pr2 match enable (tmr2ie bit) ................ 16 tmr2 to pr2 match flag (tmr2if bit) .................... 17 tmr2 to pr2 match interrupt ........................ 36, 37, 42 timing diagrams time-out sequence on power-up .............................. 60 wake-up from sleep via interrupt ........................... 65 timing diagrams and specifications ................................. 83 a/d conversion ......................................................... 89 brown-out reset (bor) ............................................. 85 capture/compare/pwm (ccp) ................................. 87 clkout and i/o ....................................................... 84 external clock ........................................................... 83 oscillator start-up timer (ost) ................................. 85 power-up timer (pwrt) ........................................... 85 reset ......................................................................... 85 timer0 and timer1 .................................................... 86 watchdog timer (wdt) ............................................. 85 w w register ......................................................................... 62 wake-up from sleep .................................................. 51, 64 interrupts ............................................................. 58, 59 mclr reset .............................................................. 59 timing diagram ......................................................... 65 wdt reset ................................................................ 59
pic16c712/716 ds41106a-page 104 preliminary 1999 microchip technology inc. watchdog timer (wdt) ............................................... 51, 63 block diagram ............................................................ 63 enable (wdte bit) ............................................... 52, 63 programming considerations .................................... 63 rc oscillator .............................................................. 63 time-out period ......................................................... 63 timing diagram .......................................................... 85 wdt reset, normal operation ...................... 54, 58, 59 wdt reset, sleep ....................................... 54, 58, 59 www, on-line support ....................................................... 3
1999 microchip technology inc. preliminary ds41106a-page 105 pic16c712/716 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103
pic16c712/716 ds41106a-page 106 preliminary 1999 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41106a pic16c712/716
pic16c712/716 ? 1999 microchip technology inc. preliminary ds41106a-page 107 pic16c712/716 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and support part no. -xx x /xx xxx pattern package temperature range frequency range device device pic16c712 (1) , pic16c712t (2) ;v dd range 4.0v to 5.5v pic16lc712 (1) , pic16lc712t (2) ;v dd range 2.5v to 5.5v pic16c716 (1) , pic16c716t (2) ;v dd range 4.0v to 5.5v pic16lc716 (1) , pic16lc716t (2) ;v dd range 2.5v to 5.5v frequency range 04 = 4 mhz 20 = 20 mhz temperature range blank = 0 c to 70 c (commercial) i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package jw = windowed cerdip so = soic p=pdip ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16c716 - 04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. b) pic16lc712 - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. c) pic16c712 - 20i/p = industrial temp., pdip package, 20mhz, normal v dd limits. note 1: c = cmos lc = low power cmos 2: t = in tape and reel - soic, ssop packages only. 3: lc extended temperature device is not offered. 4: lc is not offered at 20 mhz data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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